The present invention relates to a method for generating a test sequence for a fault in a digital circuit.
A conventional test sequence generation method is disclosed in Chapter 1, 1. 4. 2 "Stuck at Fault Testing" of a reference books entitled "FAULT TOLERANT COMPUTING THEORY AND TECHNIQUES", Volume I, issued from PRENTICE-HALL, Englewood Cliff, N.J.; and a conference document entitled "ESSENTIAL: An Effective Self-Learning Test Pattern Generation Algorithm for Sequential Circuits", IEEE Proc. Int Test Conf., pp 28-37, August 1989 and its literatures. The prior art test sequence generation method will be explained by referring to the attached drawings.
FIG. 3 shows a prior art method for generating a test sequence for a fault in a sequential circuit. In the drawing, a step 301 represents the start of the test sequence generation processing of the sequential circuit. In a step 302, the system judges whether or not there are a group of faults that are not detected yet and also that are not selected as targets of test sequences generation. When the system judges in the step 302 that there are a group of faults that are not detected yet and also that are not selected as targets of the test sequence generation, the system goes to a step 303. Otherwise, the system proceeds to a step 307.
In the step 303, the system selects a fault as a target fault from the group of faults that are not detected yet and also that are not selected as targets of the test sequence generation. In a step 304, the system performs its fault propagation processing of the target fault selected in the step 303, that is, it generates a sequence to propagate the target fault from a fault location to any external output pin, and judges whether or not its generation of the sequence was successful. If the fault propagation processing was successful, then the system goes to a step 305; whereas, if the fault propagation processing failed, then the system goes to the step 302 for processing of the next fault.
In the step 305, the system performs its state initialization processing, that is, it generates a sequence to transfer the state of the circuit from its initial state to the state of the circuit when the fault is sensitized. If generation of the sequence is successful, then the system goes to a step 306; while if it fails, then the system goes to the step 302 for processing of the next fault.
In the step 306, the system executes a fault simulation with the test sequence of the target fault selected in the step 303, and deletes the faults detected at any external output pin from the group of faults not detected yet.
FIG. 4A is a sequential circuit having three flip-flops for explaining the processing of the prior art test sequence generation method for sequential circuits. FIG. 4B is a circuit diagram for explaining the behavior of the sequential circuit of FIG. 4A when test sequence generation is carried out for a fault in the sequential circuit. FIG. 4C is a circuit diagram for explaining the behavior of the sequential circuit of FIG. 4A when the test sequence generation is carried out for another fault different from the fault in FIG. 4B. In these drawings, reference numerals 401 to 405 denote external input pins. Numeral 406 denotes an external output pin. Numerals 407 to 409 denote D flip-flops. Numerals 410 to 412 denote 2-input AND gates. Numeral 413 denotes a 2-input OR gate and 414 denotes a 2-input NOR gate. Numeral 415 denotes a stuck-at-0 fault in a signal line connected to an output of the AND gate 411. Numeral 416 denotes a stuck-at-1 fault in a signal line connected to an output of the external input pin 405. Numbers encircled by circles on the pins and gates 401 to 414 represent logical values assigned to the associated signal lines. Further, a fault signal value is expressed in the form of a fault-free value/fault value.
Explanation will next be made as to the processing of the prior art test sequence generation method for the sequential circuit by referring to FIGS. 4A to 4C.
First, the system selects the fault 415 as a target fault and performs its test sequence generation processing. As shown in FIG. 4B, the system performs its fault propagation processing to propagate the fault 415 to the external output pin 406. Since the fault 415 is of a stuck-at-0 fault, test sequence generation system traces to assign the output of AND gate 411 to logical value `1`, to assign the output of DFF 407 to logical value `1`, and to assign the output of OR gate 413 to logical value `1`. Since the D flip-flop 407 is a pseudo external input, a logical value `1` is assigned thereto. Further, in order that the output of the OR gate 413 has a logical value `1`, either one of outputs of the flip-flops 408 and 409 must have a logical value `1`. In the illustrated example, the logical value `1` is assigned to the flip-flop 408. As a result, the fault 415 is excited and the output of the AND gate 411 has a fault signal of 1/0. In order to propagate the fault signal 1/0 of the excited AND gate 411 to the external output pin 406, the logical value `1` is assigned to the input pin 405 having no fault signal because of the AND gate 412. Thus, when the output of the flip-flops 407 and 408 have both logical value `1` and the logical value `1` is provided to the external output pin 405, the fault 415 is excited and propagated to the external output pin 406.
The circuit state when the flip-flop 407 has a logical value `1` and the flip-flop 408 has a logical value `1` must be justified. First, to justify the logical value `1` of the flip-flop 407, the logical value `1` must be assigned to the external input pin 401. Since the logical value `1` is assigned to the external input pin 401, the output of the NOR gate 414 has a logical value `0`. To justify the logical value `1` of the flip-flop 408, on the other hand, the output of the gate 414 must have a logical value `1`. As a result, a conflict takes place and the system fails to find the test sequence generation for the fault 415.
Next, the system selects the fault 416 as the next target fault and performs the test sequence generation processing. As shown in FIG. 4C, the system performs its fault propagation operation to propagate the fault 416 to the external output pin 406. First, since the fault 416 is of a stuck-at-1 fault, a logical value `0` is assigned to the external output pin 405. This results in that the fault 416 is excited and a fault signal of 0/1 is propagated to the external input pin 405. In order to propagate the excited fault to the external output pin 406, the output of the gate 411 that the fault signal never reaches must have a logical value `1` because of the AND gate 412. For the output of the gate 411 to have a logical value `1`, the output of the flip-flop 407 and the output of the gate 413 must have the logical value `1`. Since the flip-flop 407 is a pseudo external input, a logical value `1` is assigned thereto. Further, for the output of the gate 413 to have a logical value `1`, either one of the outputs of the flip-flops 408 and 409 must have a logical value `1`. In this case, a logical value `1` is assigned to the flip-flop 408. Accordingly, when the output of the flip-flops 407 and 408 have respectively a logical value `1` and a logical value `0` is provided to the external output pin 405, the fault 416 is excited and propagated to the external output pin 406.
Next, the processing of justifying the circuit state that the flip-flop 407 has a logical value `1` and the flip-flop 408 has a logical value `1` is carried out. However, since it is impossible to satisfy the condition that the flip-flop 407 should have a logical value `1` and the flip-flop 408 have a logical value `1` as mentioned above, the system fails to find the test sequence generation for the fault 416.